Varicap Threshold Logic

In this paper, a highly compact novel Threshold Logic (TL) Gate approach called "Varicap TL (VcTL)" is proposed and described. The novel feature of the design is in using variable MOSFET capacitances which reduces the area. The electrical analysis of this variable MOSFET capacitance is presented and its variability is explained. Varicap TL (VcTL) gate is created by using a latch type decision circuit topology. Parallel counter implementations of (7,3) in 0.13 mu m and 0.18 mu m technology are realized by using proposed Varicap TL based on Minnick TL Network. Comparison of these implementations with Boolean Logic (BL) based dynamic (7,3) counter is shown. VcTL approach in 0.13 mu m offers 41% smaller area which is a significant result of the approach and 27% higher speed and only 24% higher power consumption compared to BL realization in 0.13 mu m technology. The results also show VcTL's scalability. As VcTL is scaled from 0.18 mu m to 0.13 mu m, the speed is increased by 21%, the area is decreased by 33% and power by 37%.