Static Memory Design

In this chapter, we explore the design of static memory structures. We start with the description of the operation of the single-port six-transistor SRAM cell. Subsequently, we discuss issues related to the design of memory peripherals such as voltage-mode and current-mode differential reads, single-ended reads, and control logic. We present design techniques to reduce SRAM dynamic and static power. We also cover issues pertaining to SRAM reliability, testing, and yield. Subsequently, we show how to implement efficient multi-port register file storage cells and peripherals and we present an example of replica-based self-timed control logic.