Routing for FPGAs

In Chapter 3, technology mapping in CAD systems for FPGAs was discussed in detail. The next step in such systems is the placement of the logic blocks. This problem in the FPGA environment is very similar to placement tasks for other technologies, for example standard cells. A number of efficient techniques for placement have already been developed and well documented in the technical literature [Hana72] [Sech87]. Since these techniques can easily be adapted to use for FPGAs, we will not pursue the placement task in this book. This chapter focuses on the next step in the CAD system, where the routing of interconnections among the logic blocks is realized. As Figure 5.1 indicates, routing is the final phase of a circuit’s implementation, after which the FPGA can be configured by a programming unit.