Industrial Clock Design

Power and variation are the biggest concerns of physical design today. Clock distribution network is at the center of both the power and variation concerns. Clock distribution networks consume a lion's share of the total IC power consumption for two reasons. First, the clock distribution network requires many large buffers to deliver crisp clock signals across a large area of the IC. Second, the clock distribution network uses many small buffers to balance the clock skews. Clock distribution networks are also most susceptible to variation for two reasons. First, both the latency and length of a clock path are usually much longer than those of typical timing paths. Second, variations to clock path delays may have a 2X impact to the timing of a timing path. Let's consider a timing path between a launching and a capturing flop and suppose that the clock path to the launching flop is sped up by 100ps and the clock path to the capturing flop is slowed down by 100ps due to variation. The impact to the hold constraint of the timing path would be 200ps. Our customers have seen chip failures due to hold violations caused by variation in this manner. Therefore, for 45nm technology nodes and beyond, we believe that a power-efficient and variation-tolerant clock distribution network is a necessary condition for a competitive IC product. In this talk we discuss the industrial clock design problems, designers' strategies for resolving the problems and the capabilities of commercial tools that we must provide to support the designers.