A 2GSPS 6-bit two-channel-interleaved successive approximation ADC design in 65nm CMOS

This paper presents a two channel interleaved 6-bit 2GS/s successive approximation (SA) analog-to-digital converter design. The proposed SAR-ADC employs different comparators for each stage, which eliminates digital control delay as in conventional design. Using small size of capacitor and pre amplified comparator, the sampling rate limitation has been broken up with which is only related to intrinsic delay of this circuit. Error correction technique and mismatch calibration relax the requirement of comparator which in end minimizes power consumption. It achieves a peak SNDR of 31.8dB and 29.1dB, at 1.5GS/s and 2GS/s, consuming 9.13mW and 12.58mW with a unit capacitance of 15fF. © 2013 IEEE.