Testing Methodology of Embedded DRAMs
Santa Clara, CA（2012）
摘要
The embedded-DRAM (eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Finally, we propose a mathematical model to estimate the defect level caused by wear-out defects under the use of error-correction-code circuitry, which is a special function used in eDRAMs compared to commodity DRAMs. The experimental results are collected based on 1-lot wafers with an 16 Mb eDRAM core.
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关键词
switch transistor,integrated circuit testing,sram testing,dram cell,1t-sram architecture,sram interface,error-correction-code,total test time,dram testing,embedded-dram (edram),sram chips,edram core,mathematical model,mathematical analysis,error-correction-code circuitry,embedded drams,embedded dram testing methodology,testing methodology,dram chips,retention-fault coverage,retention,fault model,mb edram core,wear-out defects,test algorithm,leakage mechanisms,1-lot wafers,1-lot wafer,dram cells,edram testing,transistors,couplings,fault coverage,error correction code,testing,special functions,capacitors
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