A Chip Architecture for Compressive Sensing Based Detection of IC Trojans

Yi-Min Tsai,Keng-Yen Huang,H. T. Kung,Dario Vlah,Youngjune L. Gwon,Liang-Gee Chen

Signal Processing Systems（2012）

引用 5|浏览0

暂无评分

摘要

We present a chip architecture for a compressive sensing based method that can be used in conjunction with the JTAG standard to detect IC Trojans. The proposed architecture compresses chip output resulting from a large number of test vectors applied to a circuit under test (CUT). We describe our designs in sensing leakage power, computing random linear combinations under compressive sensing, and piggybacking these new functionalities on JTAG. Our architecture achieves approximately a 10X speedup and 1000X reduction in output bandwidth while incurring a small area overhead.

查看译文

关键词

proposed architecture compresses chip,leakage power,invasive software,piggybacking,integrated circuit testing,test vectors,chip architecture,output bandwidth,new functionalities,compressive sensing,leakage power sensing design,large number,jtag standard,cs-jtag,compressed sensing,measurement generator,ic trojan,small area overhead,cut,random linear combination,random linear combinations,compressive sensing method,circuit under test,ic trojan detection,cs

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要