A method for detecting interconnect DSM defects in systems on chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems（2006）
摘要
This paper presents a built-in test method targeting interconnect defects using IDDT testing, delay testing, and boundary scan. It was learned that IDDT testing is an effective way to detect open and short defects. Boundary scan can provide accessibility to internal buses inside a chip. A statistical analysis method eases the uncertain factors due to process variations and power fluctuation. This paper also includes the experimental data using the proposed techniques to detect shorts, opens, or the other non-stuck-at fault type defects.
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关键词
short defect,internal buses,non-stuck-at fault type defect,systems on chip,built-in test method,integrated circuit testing,integrated circuit interconnections,proposed technique,bus interconnect testing,statistical analysis method,statistical analysis,delay testing,internal bus,iddt testing,dsm defect,power fluctuation,system-on-chip,experimental data,boundary scan testing,built-in self test,BIST,SOC,nonstuck at fault type defects,defect models,TAP,boundary scan,DSM,interconnect DSM defects detection
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