An 8-bit 19MS/s low-power 0.35µm CMOS pipelined ADC for DVB-H

AbstractThis paper proposes an 8b 19MHz CMOS pipelined analog-to-digital converter (ADC) for DVB-H. In order to reduce the power consumption a combination of techniques has been used, such as op-amp sharing, low-power amplifiers with gain boosting and an aggressive capacitor scaling. The prototype ADC fabricated in [email protected] CMOS demonstrates a maximum differential nonlinearity (DNL) of 0.63 least significant bit (LSB) and a maximum integral nonlinearity (INL) of 0.58 LSB with a peak signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 42.76 and 51.57dB at 19MHz. The ADC with an active area of 4.78mm^2 consumes less than 4mW at the mentioned sampling frequency.