Delayed Latching for Data Synchronization in GALS SOC

Globally asynchronous, locally synchronous (GALS) systems-on-chip (SoCs) may be prone to synchronization failure. This paper presents an in-depth analysis of the problem and proposes a novel solution. The problem is analyzed considering the cycle times of the GALS module, and the complexity of the asynchronous interface controllers using Petri Net graph (PN) approach. When high data bandwidth is not required, matched-delay asynchronous ports may be employed. A novel architecture for synchronizing inter-modular communications in GALS, based on delayed latching (DL), is described. DL synchronization does not require pausable clocking, is insensitive to clock tree delays, and supports high data rates. It replaces complex global timing constraints with simpler localized ones. Decoupled input port and Decoupled output port for Delayed Latching are presented. The risk of metastability in the synchronizer is analyzed in a technology-independent manner. Here we present the Petri net models of the Globally Asynchronous and Locally Synchronous (GALS) architectures for speed independent (SI). The models are feed into Petrify to produce logic equations for gate level implementation of asynchronous circuit. The circuit is simulated on VCS and synthesized on Design compiler of Synopsys EDA tool.