Low power, high throughput network-on-chip fabric for 3D multicore processors
Computer Design（2011）
摘要
Long wires degrade significantly the performance of network-on-chip (NoC) communication fabric in large multicore processors. 3D network-on-chip architecture alleviates the problem of long wires, but practical limitations of CMOS technology restrict such structures to two active layers only. In this work, we study a heterogeneous 3D chip with processor cores and cache blocks implemented in CMOS and NoC fabric in VeSFET tech-nology. Such a 3D architecture shows significant improvements in all network parameters including latency, power and energy consumption compared to existing 3D NoCs.
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关键词
CMOS integrated circuits,integrated circuit design,multiprocessing systems,network-on-chip,3D multicore processor,3D network-on-chip architecture,CMOS technology,NoC communication fabric,VeSFET technology,cache block,energy consumption,heterogeneous 3D chip,long wires,network parameter,processor cores,3D NoC,3D multi-core processsor,VeSFET
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