A High Speed Parallel Timing Recovery Algorithm and Its FPGA Implementation

The paper presents an efficient and parallel symbol timing recovery algorithm suitable for very high speed demodulator and easy to implement on FPGA platform. The proposed timing recovery algorithm has a dual feedback structure which makes up of frequency domain timing phase correction, first reported in Alternate Parallel Receiver (APRX), and parallel FIFOs based delete-keep algorithm. In the timing error detector, we adopt the O\&M algorithm. We also investigate their high speed parallel implementation structures suitable for FPGA platform. The fixed point simulation shows that our proposed algorithm can work efficiently with performance loss less than 0.5dB. Besides, the algorithm is implemented with a Xilinx XC6VLX240T FPGA chip, and reaches the maximum running frequency of 188 MHz. Thus, it sustains a symbol rate of 1.5 Gsps when 4 samples per symbol are employed.