Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

Won-Ho Choi,Jungwoo Oh,Ook-Sang Yoo,In-Shik Han,Min-Ki Na,Hyuk-Min Kwon,Byung-Suk Park,P. Majhi,H. -H. Tseng,R. Jammy,Hi-Deok Lee

Microelectronic Engineering（2011）

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摘要

Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.

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关键词

improved transport characteristic,ge epitaxy,silicon passivation technique,interface trap density,device performance,analyzed herein,high- k metal gate,nbti,si ipl improved charge,ge pmosfets,lower trap density,si ipl,si interface passivation layer,high performance,si passivation,bulk trap density,high k metal gate,field effect transistor

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