Design of Asynchronous Circuits on FPGAs for Soft Error Tolerance
Digital System Design（2011）
摘要
In this paper, we investigate the mechanism of soft error generation, propagation in asynchronous circuits which are implemented on FPGA. We also proposed the circuit to detect the soft errors which propagate in asynchronous Pipelines. The effects of the soft errors on Quasi-delay-insensitive (QDI) asynchronous circuits are analyzed and detected. The simulation results show that the proposed detect circuit can detect the soft error in asynchronous circuits implemented on FPGAs easily so that FPGAs can be reprogrammed, compared with traditional synchronous circuits.
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关键词
asynchronous pipelines,asynchronous circuit,soft error generation,asynchronous circuit design,traditional synchronous circuit,quasidelay-insensitive asynchronous circuits,logic design,detection circuit,fpga,asynchronous circuits,simulation result,field programmable gate arrays,soft error tolerance,soft error,pipelines,logic gates,logic gate,field programmable gate array
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