IBM POWER7 processor circuit design

D. F. Wendel,J. Barth,D. M. Dreps,S. Islam,J. Pille,J. A. Tierno

IBM Journal of Research and Development（2011）

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摘要

The IBM POWER7® processor contains many innovative circuit ideas that enable advanced architectural features. A high-density embedded dynamic random access memory is used to provide 32 MB of level-3 cache. Improved input/output (I/O) links provide up to 50 GB/s of I/O bandwidth. An innovative phase-locked loop design allows for dynamic, per-core frequency variation, and unique multiport techniques for register files as well as six-transistor cell-based memory cells to support the superscalar multithreaded out-of-order processor.

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关键词

ibm power7 processor circuit,superscalar multithreaded out-of-order processor,embedded dynamic random access,ibm power7,innovative phase-locked loop design,improved input,six-transistor cell-based memory cell,o bandwidth,architectural feature,level-3 cache,innovative circuit idea

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