BE-TANOS: Feasibility and technology limitations

The aim of this work is to investigate the physical mechanisms behind the write/erase and retention performances of band gap engineering (BE) layers used as tunnel oxide in charge trap memory stack. The investigation of the BE layers alone will be completed with the analyses of its integration within a TANOS (TaN/Alumina/Nitride/Oxide/Silicon) stack, pointing out the correlation between electrical performance and reliability limits. Good write/erase/retention performances can be achieved with BE tunnel oxide by using silicon nitride layer integrated in SiO"2-Si"3N"4-SiO"2 stack, as long as all different mechanisms are taken into account in optimizing stack composition: hole injection which improves erase efficiency, charge trapping and de-trapping from the thin silicon nitride which causes program instabilities and initial charge loss which does not significantly impact long term retention. All these phenomena make very crucial the BE tunnel process control and difficult its use for multi-level application.