On-chip interconnect analysis of performance and energy metrics under different design goals
IEEE Transactions on Very Large Scale Integration (VLSI) Systems（2011）
摘要
As semiconductor process technology scales down, interconnect planning presents ever-greater challenges to designers. In this paper, we analyze, evaluate, and compare various metrics with optimized wire configurations in the contexts of different design criteria: delay minimization, delay-power minimization, and delay2 -power minimization. We show how various design criteria influence the configuration, performance, and power consumption of repeated wires.
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关键词
power minimization,ever-greater challenge,different design goal,various design criterion,delay minimization,repeated wire,delay-power minimization,various metrics,power consumption,optimized wire configuration,energy metrics,different design criterion,leakage current,fault detection,integrated circuit design,fault coverage,analysis,random testing,interconnect,design optimization,repeaters,process model,minimization,chip
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