Overview of a compiler for synthesizing MATLAB programs onto FPGAs

Prithviraj Banerjee,Malay Haldar,Anshuman Nayak,Victor Kim,Vikram Saxena,Steven Parkes,Debabrata Bagchi,Satrajit Pal,Nikhil Tripathi,David Zaretsky,Robert Anderson,Juan Ramon Uribe

IEEE Transactions on Very Large Scale Integration (VLSI) Systems（2004）

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摘要

This paper describes a behavioral synthesis tool called AccelFPGA which reads in high-level descriptions of digital signal processing (DSP) applications written in MATLAB, and automatically generates synthesizable register transfer level (RTL) models and simulation testbenches in VHDL or Verilog. The RTL models can be synthesized using commercial logic synthesis tools and place and route tools ont...

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关键词

synthesizing matlab program,field programmable gate arrays,logic synthesis,register transfer level,modeling and simulation,logic design,high level synthesis,digital signal processing,signal generators,field programmable gate array,vhdl,mathematical model,hardware description languages,place and route

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