Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design
IEEE Design & Test of Computers（2011）
Key words
SRAM chips,embedded systems,low-power electronics,scaling circuits,SRAM scaling,bit cell optimizations,circuit techniques,embedded memory,low voltages,nanoscale SRAM design,robust operation,six-transistor SRAM cells,SRAM,VCCmin,design and test,high-performance applications,low power,minimum operating voltage
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