A unified design space simulation environment for network-on-chip: fuse-N.

Current uni-processor centric modelling methodology does not address the new design challenges introduced by MPSoCs, thus, calling for efficient simulation frameworks capable of capturing the interplay between the application, the architecture, and the network. Addressing these new challenges requires a framework that assists the designer at different abstraction levels of system design. This paper concentrates on developing a framework for unified simulation environment for NoCs (fuse-N), which simplifies the design space exploration for NoCs by offering a comprehensive simulation support. The framework synthesises the network infrastructure and the communication model and optimises application mapping for design constraints. The paper also proposes an efficient traffic aware scheduling algorithm that optimises the mapping problem by dynamically determining the latency by considering the communication and execution costs. The framework follows a top-down paradigm, where each design space component is implemented as modular components and all design constraints are captured and evaluated coherently. The proposed framework is a hardware-software co-design implementation using SystemC 2.1 and C++. Simulation results show the various design space explorations that can be performed by our framework.