Statistical analysis of hold time violations

Performance variability is increasing as CMOS devices are continuously scaled down to nanometer dimensions and is posing a major challenge to the profitability of scaled technologies. One of the major goals of a design flow is to satisfy timing constraints without sacrificing area and power. One of the most important tasks of design optimization is to identify and remove setup and hold time violations. Variability issues must be taken into account in order to improve the accuracy of violation removal algorithm. In this manuscript we derive statistical models for flip-flop race immunity and clock skew. Then we propose a probabilistic approach for hold-time violations. We present comparisons between probabilistic approach and worst-case approach and prove that the probabilistic method is less pessimistic while being more accurate. We propose a variation-aware methodology for computing the delay so as to satisfy the yield constraint.