A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit

Xiao Yan Zhang,Yiu-Hing Chan, Robert Montoye,Leon Sigal,Eric Schwarz, Michael Kelly

Journal of Signal Processing Systems（2009）

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摘要

A power and area efficient 108-bit end-around carry adder is implemented using IBM 65nm SOI technology. The adder is used for a multiply-add fused (MAF) floating point unit. Careful balance of the adder structure and structure-aware layout techniques enabled this adder to have a latency of 270ps at power consumption of 20mW with 1V supply.

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关键词

Adder,Floating-point,Multiply-add fused,End-around carry

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