Efficient Power Network Analysis Considering Multidomain Clock Gating

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(2009)

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摘要
In this paper, an efficient framework is proposed to analyze the worst case of voltage variation of power network considering multidomain clock gating. First, a frequency-domain-based simulation method is proposed to obtain the time-domain voltage response. With the vector fitting technique, the frequency-domain responses are approximated by a partial fraction expression, which can be easily converted to a time-domain waveform. Then, an algorithm is proposed to find the worst-case voltage variation and corresponding clock gating patterns, through superimposing the voltage responses caused by all domains working separately. The major computation of the whole framework is solving the frequency-domain equation system, whose complexity is about O(NalphaD log f max), where alpha is between one and two if using an iterative solver from the PETSc library. N is the node number, f max is the upper bound of frequency, and D is the number of clock domains. Numerical results show that the proposed simulation method is up to several hundred times faster than commercial fast simulators, like HSPICE and MSPICE. In addition, the proposed method is able to analyze large-scale power networks that the commercial tools are not able to afford.
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关键词
logic circuits,SPICE,HSPICE,power network analysis,PETSc library,partial fraction expression,frequency-domain analysis,vector fitting (VF),proposed simulation method,multidomain clock gating,clocks,MSPICE,Frequency-domain analysis,time-domain analysis,voltage response,clock domain,efficient power network analysis,vector fitting technique,iterative solver,power network,transmission networks,voltage variation,numerical simulation method,time-domain voltage response,distribution networks,worst-case voltage variation,frequency-domain-based simulation method,node number,iterative methods,corresponding clock
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