A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3- $\mu\hbox{m}$ LTPS-TFT Technology

A phase-locked loop (PLL) with self-calibrated charge pumps (CPs) has been fabricated in a 3-mum low-temperature polysilicon thin-film transistor (LTPS-TFT) technology. A voltage scaler and self-calibrated CPs are used to reduce the static phase error, reference spur, and jitter of an LTPS-TFT PLL. This PLL operates from 5.6 to 10.5 MHz at a supply of 8.4 V. Its area is 18.9 mm2, and it consumes 7...