Three-Transistor DRAM-Based Content Addressable Memory Design for Reliability and Area Efficiency

Content addressable memory is widely used in communication network, inference machine and cache system. In this paper a three-transistor DRAM-based content ad-dressable memory cell design is proposed based on the Berger and m-out-of-n codes. The coding cannot only approve to reduce the redundant transistors but also provide a totally self-check for refresh and error detec-tion mechanism for reliability. A novel Berger invert code is presented for improve the dependability for about 21% and information energy for 25%. From a variety of post-layout SPICE simulations, the search-match delay time cab be controlled under typical DRAM-based CAM level and the area efficient can be improved by almost double.