Wafer-Level 3d Integration Technology

S. J. Koester, A. M. Young, R. R. Yu,S. Purushothaman, K. -N. Chen,D. C. La Tulipe,N. Rana,L. Shi, M. R. Wordeman, E. J. Sprogis

IBM JOURNAL OF RESEARCH AND DEVELOPMENT（2008）

引用 158|浏览0

暂无评分

摘要

An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed.

查看译文

关键词

process technology element,integration scheme,production environment,basic reasoning,detailed description,possible process variation,integration technology,integrated circuit,wafer-level integration scheme

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要