High Speed k-Winner-Take-ALL Competitive Learning in Reconfigurable Hardware

A novel hardware architecture of the competitive learning (CL) algorithm with k -winners-take-all activation is presented in this paper. It is used as a custom logic block in the arithmetic logic unit (ALU) of the softcore NIOS processor for CL training. Both the partial distance search (PDS) module and hardware divider adopt finite precision calculation for area cost reduction at the expense of slight degradation in training performance. The PDS module also employs subspace search and multiple-coefficient accumulation techniques for effective reduction of the computation latency for the PDS search. Experiment results show that the CPU time is lower than that of Pentium IV processors running the CL training program without the support of custom hardware.