An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs

SoC verification efforts involve multiple models of the design - RTL, FPGA, silicon and software models. With increasing design complexity, re-use of tests between models is a must. In this paper, we introduce a stimulus abstraction mechanism which greatly increases the re-usability of tests across models. We then demonstrate an implementation of the abstraction mechanism on two models of a PCI-Express based design. Identical tests are used to drive an RTL model via a BFM and a software model via stream sockets to achieve the same result.