Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology
Bratislava（2008）
摘要
This paper examines three different flip-flop designs in subthreshold operation. All flip-flops are simulated in a 65 nm and 90 nm process with a supply voltage ranging from 125 mV to 1 V. Process variations are examined at different process corners Successful operations of a PowerPC 603 flip-flop at all process corners with a supply voltage down to 125 mV is shown at 65 nm. The best PDP and EDP numbers of flip-flops design at VDD = 200mV in this paper are 53.6 aJ and 0.88 yJs, respectively.
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关键词
subthreshold flip-flop,edp number,best pdp,different flip-flop design,nm cmos technology,different process corner,flip-flops design,v. process variation,successful operation,nm process,process corner,supply voltage,informatics,integrated circuit design,process variation,circuits,power dissipation,cmos technology,leakage current,application software,cmos integrated circuits,threshold voltage
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