A Stacked NoC Architecture for Quality-of-Service
Information Science and Engineering, 2008. ISISE '08. International Symposium（2008）
摘要
As CMOS technology enters sub-micron era, a large number of intelligent properties (IPs) are integrated on a single chip (SoC). The communication patterns become difficult to model. At the same time, as transistors become small and wires become narrow, delays are becoming more and more unpredictable. The factors greatly challenge traditional on-chip buses and point-to-point interconnects because of their problems of scalability and flexibility. In the paper, we propose a stacked on-chip network architecture to provide reliable and efficient on-chip communication in SoCs. The architecture uses a delay-insensitive asynchronous physical channel control scheme and reserved virtual channel control scheme to guarantee the quality-of-service of the on-chip network.
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关键词
intelligent property,on-chip network architecture,delay-insensitive asynchronous,communication pattern,efficient on-chip communication,traditional on-chip bus,on-chip network,virtual channel control scheme,cmos technology,stacked noc architecture,physical channel control scheme,quality of service,logic design,asynchronous logic,network on chip,transistors,cmos integrated circuits,integrated circuit design,protocols,network on a chip,synchronization,chip,network architecture,point to point,physical layer,soc
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