Case study of reliability-aware and low-power design

Shengqi Yang,Wenping Wang,Tiehan Lu,Wayne Wolf,N. Vijaykrishnan,Yuan Xie

IEEE Transactions on Very Large Scale Integration (VLSI) Systems（2008）

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摘要

Based on the proposed reliability characterization model, reliability-aware and low-power design is illustrated for the first time as a design methodology to balance reliability enhancement and power reduction. Low-power and reliable SRAM cell design, reliable dynamic voltage scaling (DVS) algorithm design, and voltage island partitioning and floorplanning for reliable system-on-a-chip (SOC) design are demonstrated as case studies of this new design methodology.

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关键词

voltage island partitioning,reliable sram cell design,reliable dynamic voltage scaling,proposed reliability characterization model,low-power design,algorithm design,reliability enhancement,reliable system-on-a-chip,design methodology,case study,new design methodology,floorplanning,low power electronics,circuits,integrated circuit layout,system on a chip,reliability engineering,sram,system on chip,algorithm design and analysis

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