High Speed Ultra Low Voltage CMOS inverter

Yngvar Berg,Omid Mirmotahari,Johannes Goplen Lomsdalen,Snorre Aunet

Montpellier（2008）

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摘要

In this paper we discuss timing details and performance of the ultra low voltage (ULV) logic style [3]. The ULV logic gates can be utilized to design high speed systems operating at ultra low supply voltages. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offsets voltages are used to shift the effective threshold voltage of the evaluating transistors. The simulated data presented is obtained using the Spectre simulator provided by Cadence and valid for a 90nm CMOS process.

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关键词

CMOS integrated circuits,high-speed integrated circuits,invertors,low-power electronics,CMOS process,Spectre simulator,ULV,effective threshold voltage,high speed ultra low voltage CMOS inverter,offsets voltages,semi-floating-gate nodes,size 90 nm,ultra low voltage logic dates,CMOS,Low voltage,high speed,inverter,semi floating-gate

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