A reconfigurable application specific instruction set processor for convolutional and turbo decoding in a SDR environment

Future mobile and wireless communication networks require flexible modem architectures to support seamless services between different network standards. Hence, a common hardware platform that can support multiple protocols implemented or controlled by software, generally referred to as software defined radio (SDR), is essential. This paper presents a family of dynamically reconfigurable application-specific instruction-set processors (ASIP) for the application domain of channel coding in wireless communication systems. As a weakly programmable IP core, it can implement trellis based channel decoding in a SDR environment. It features binary convolutional decoding, and turbo decoding for binary as well as duobinary turbo codes for all current and upcoming standards. The ASIPs consist of a specialized pipeline with 15 stages and a dedicated communication and memory infrastructure. Logic synthesis revealed a maximum clock frequency of 400 MHz and a total area of 0.42 mm2 for a 65 nm technology. Simulation results for Viterbi and turbo decoding demonstrate maximum throughput of 196 and 34 Mbps, respectively, and outperforms existing SDR based approaches for channel decoding.