Understanding the Performance of Sparse Matrix-Vector Multiplication

In this paper we revisit the performance issues of the widely used sparse matrix-vector multiplication kernel on modern microarchitectures. Previous scientific work reports a number of different factors that may significantly reduce performance. However, the interaction of these factors with the underlying architectural characteristics is not clearly understood, a fact that may lead to misguided and thus unsuccessful attempts for optimization. In order to gain an insight on the details of performance, we conduct a suite of experiments on a rich set of matrices for three different commodity hardware platforms. Based on our experiments we extractuseful conclusions that can serve as guidelines for the subsequent optimization process of the kernel.