Designing CMOS Circuits for Switch-Level Testability

Conventional testing techniques often fail to be effective for CMOS combinational circuits, since most of their switch-levelfaults cannot be detected by stuck-at-fault testing. The alternative is to design for testability. The design techniques presentedhere for fully testable CMOS combinational circuits use a three-pattern test scheme to detect both stuck-open and stuck-onswitch-level faults. The circuit is implemented with specially designed gates that have no undetectable stuck-on faults. Aninverting buffer is inserted between logic gates, and two FETs are added to each logic gate to make it testable for stuck-onfaults.