Improving Gate-Level ATPG by Traversing Concurrent EFSMs

The paper describes an high-level pseudo-deterministic ATPG that explores the DUT state space by exploiting an easy-totraverse extended FSM model. Testing of hard-to-detect faults is thus improved. Generated test sequences are very effective in detecting both high-level faults and gate-level stuck-at faults. Thus, the reuse of test sequences generated by the proposed ATPG allows to improve the stuck-at fault coverage and to reduce the execution time of commercial gate-level ATPGs.