At-speed logic BIST architecture for multi-clock designs

Laung-Terng Wang,Xiaoqing Wen,Po-Ching Hsu,Shianling Wu,Jonhson Guo

2005 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS（2005）

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摘要

This paper presents an at-speed logic BIST architecture for testing multi-clock, multi-frequency designs. The scheme employed allows true at-speed test quality for circuits containing multiple clocks without any clock frequency manipulation. Physical implementation is easily achieved due to the use of a low-speed scan enable (SE) signal and reduced timing-critical design requirements. Application results for two industrial designs are also reported.

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关键词

low-speed scan enable signal,at-speed logic bist architecture,application result,multi-frequency design,boundary scan testing,multi-frequency designs,built-in self test,clocks,multi-clock testing,timing-critical design requirement,true at-speed test quality,circuits testing,multi-clock designs,at-speed test quality,timing-critical design requirements,physical implementation,industrial design,multiple clock,circuit testing,clock frequency manipulation,logic testing

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