Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators
IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: NEW FRONTIERS IN VLSI DESIGN（2005）
摘要
Among many recently proposed on-chip jitter measurement designs, vernier delay line (VDL) is one of the most widely adopted methods that can achieve fine resolution. However, there are two major design challenges: the first is the mismatching of delay buffers; the second is the unavailability of an on-chip jitter free reference signal. To overcome these two challenges, we propose a self-refereed on-chip jitter measurement circuit. This measurement circuit eliminates the requirement to a jitter free reference signal. In addition, it utilizes vernier oscillators to alleviate the mismatching effect in vernier lines. Using this design, the jitter distribution and jitter RMS value can be characterized. To validate the design, the circuit has been implemented using IBM 7HP 0.18um CMOS technology.
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关键词
vernier line,self-refereed on-chip jitter measurement,jitter rms value,jitter free reference signal,vernier oscillators,measurement circuit,jitter distribution,vernier delay line,major design challenge,on-chip jitter measurement design,on-chip jitter free reference,cmos integrated circuits,cmos technology,circuit design,jitter,system on chip,chip,oscillations,vdl,oscillators,cmos,integrated circuit design
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