Leakage-Aware Interconnect for On-Chip Network

Yuh-Fang Tsai,Vijaykrishnan Narayaynan,Yuan Xie,Mary Jane Irwin

CoRR（2005）

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摘要

On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes. Our schemes achieve 10.13%~63.57% active leakage savings and 12.35%~95.96% standby leakage savings across schemes while the delay penalty ranges from 0% to 4.69%.

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关键词

on-chip network,delay penalty range,leakage-aware interconnect,future systems-on-chip,active leakage saving,significant portion,main constraint,standby leakage saving,power budget,system on chip,chip,low power electronics,system on a chip,wireless sensor network,network on a chip,set cover,noc,coverage,threshold voltage

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