Design and test of a 9-port SRAM for a 100 Gb/s STS-1 switch

R G Gibbins, R D Adams,Thomas J Eckenrode, Michael R Ouellette,Yuejian Wu

MTDT '02 Proceedings of the The 2002 IEEE International Workshop on Memory Technology, Design and Testing（2002）

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摘要

This paper presents the design, fault modeling, and BIST solution of an application specific 9-port SRAM. The use of the 9-port SRAM in place of more conventional memory in a 100 Gb/s SONET switch ASIC resulted in calculated reductions of 43% in die size, 31% in power consumption and 75% in data memory bit count. A custom programmable BIST solution was implemented that takes into consideration the memory's special features such as the large number of ports, large read-to-write port asymmetry and the TDM read scheme.

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关键词

sonet,sram chips,application specific integrated circuits,built-in self test,fault simulation,packet switching,100 gbit/s,9-port sram,bist solution,sts-1 switch,tdm read scheme,application specific ic,custom programmable solution,data memory bit count,die size,fault modeling,power consumption,read-to-write port asymmetry,time division multiplexing,decoding,microelectronics,testing,fault model,switches

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