Implementing Neon: A 256-Bit Graphics Accelerator

IEEE Micro(1999)

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摘要
High-performance 3D graphics accelerators traditionally require multiple chips on multiple boards. In contrast, Neon is a single chip that performs like a multichip design. Neon accelerates OpenGL 3D rendering, and X11 and Windows/NT 2D rendering. Since our pin budget limited memory bandwidth, we designed Neon from the memory system upward to reduce bandwidth requirements. To fit our gate budget, we shared logic among different operations with similar implementation requirements, and left floating point calculations to Digital's Alpha CPUs. Neon-based boards compete well against other workstation accelerators, but cost much less due to a small part count and use of commodity SDRAMs.
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关键词
Acceleration,Bandwidth,Prefetching,Rendering (computer graphics),Workstations,Computer graphics,Logic arrays,Application specific integrated circuits,SDRAM,Software performance
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