Transistor sizing issues and tool for multi-threshold CMOS technology
Anaheim, CA, USA（1997）
摘要
Multi-threshold CMOS is an increasingly popular circuitapproach that enables high performance and low power operation.However, no methodologies have been developed to size the highV{t} sleep transistor in an intelligent manner that trades off area andperformance. In fact, many attempts at sizing the sleep transistorwithout close consideration of input vector patterns or internalstructures can lead to large overestimates or large underestimatesin sleep transistor sizing. This paper describes some of the issuesinvolved in sizing transistors for MTCMOS and also introduces avariable breakpoint switch level simulator that can rapidly calculatedelay in MTCMOS circuits as functions of design variablessuch as V{dd}, V{t}, and sleep transistor sizing.
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关键词
multi-threshold cmos,sleep transistorwithout close consideration,transistor sizing issue,area andperformance,large underestimatesin,large overestimate,sizing transistor,multi-threshold cmos technology,design variablessuch,mtcmos circuit,transistor sizing,avariable breakpoint switch level,capacitance,cmos technology,voltage,switches,integer linear programming,covering problems
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