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Zhuo Li

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EARLY DESIGN CYCLE OPTIMZATION

Charles J Alpert, Robert M Averill,Zhuo Li, Jose L P Neves,Stephen T Quay

(2014)

Cited by6Bibtex

Physical synthesis optimization with fast metric check

Charles J Alpert, Glenn R Bee,Zhuo Li, Tuhin Mahmud,Stephen T Quay, Lakshmi N Reddy,Chin Ngai Sze,Yaoguang Wei

(2014)

Cited by2Bibtex

Automatic Generation of Wire Tag Lists for a Metal Stack

Charles J Alpert, Robert M Averill,Eric J Fluhr,Zhuo Li, Tuhin Mahmud, Jose L P Neves,Stephen T Quay,Chin Ngai Sze,Yaoguang Wei

(2014)

Cited by4Bibtex

Resolving global coupling timing and slew violations for buffer-dominated designs

Charles J Alpert, Clabes G Joachim,Zhuo Li, Tuhin Mahmud,Stephen T Quay

(2013)

Cited by5Bibtex

Timing driven routing in integrated circuit design

Charles J Alpert,Zhuo Li,Stephen T Quay, Ying Zhou

(2013)

Cited by4Bibtex

TECHNIQUES FOR SUPER FAST BUFFER INSERTION

Charles J Alpert,Zhuo Li,Stephen T Quay

(2008)

Cited by11Bibtex

Techniques for Fast Physical Synthesis Fast, efficient buffer design, logic transformations, and clustering components for placement are some of the techniques being used to reduce design turnaround for large, complex chips

Charles J Alpert,Shrirang K Karandikar,Zhuo Li,Gijoon Nam,Stephen T Quay,Haoxing Ren,Member Ieee,C N Sze,Paul G Villarrubia,Mehmet Can Yildiz

(2007)

Bibtex

Techniques for Fast Physical Synthesis

Charles J. Alpert,Shrirang K. Karandikar,Zhuo Li,Gi-Joon Nam,Stephen T. Quay,Haoxing Ren,C. N. Sze,Paul G. Villarrubia,Mehmet C. Yildiz

Proceedings of the IEEE, no. 3 (2007): 573-599

Cited by69EIBibtex

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