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Yoshinori Nishi (Member, IEEE) received the B.S. and M.S. degrees in low-temperature physics from Waseda University, Tokyo, Japan, in 1997 and 1999, respectively.
From 1999 to 2003, he was with NTT Electronics Inc., Atsugi, Japan, as a Member of the Ultrahigh-Speed Device Development Group, where he was a Chief Designer for the 50Gb/s InP HEMT logic family, first 50Gb/s product in the market in 2001. In 2003, he joined Kawasaki Microelectronics Inc., Chiba, Japan, Research and Development Division, where he led the development of 10 Gb/s burst-mode CDR for 10G-EPON application as a Chief Architect, also first in the market in 2009. He joined NVIDIA Corporation, Santa Clara, CA, USA, in 2011, and led one of the NVLINK physical layer (PHY) design teams for eight years before he joined NVIDIA Research in 2020. His current research focuses on ultralow power and high-density interconnect for short-reach applications.
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VLSI Technology and Circuitsno. 99 (2023): 1-2
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