Xinyu Niu

Imperial College London, London, United Kingdom

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Papers51 papers

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Optimizing Reconfigurable Recurrent Neural Networks

Zhiqiang Que,Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng,Xinyu Niu,Wayne Luk

FCCM, pp.10-18, (2020)

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On the challenges in programming mixed-precision deep neural networks

Ruizhe Zhao,Wayne Luk, Chao Xiong,Xinyu Niu, Kuen Hung Tsoi

PLDI '20: 41st ACM SIGPLAN International Conference on Programming Language Design and Implementatio..., pp.20-28, (2020)

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F-E3D - FPGA-based Acceleration of an Efficient 3D Convolutional Neural Network for Human Action Recognition

Hongxiang Fan, Cheng Luo, Chenglong Zeng, Martin Ferianc, Zhiqiang Que, Shuanglong Liu, Xinyu Niu, Wayne Luk

ASAP, pp.1-8, (2019)

Cited by4EIBibtex

Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going

Erwei Wang,James J. Davis, Ruizhe Zhao,Ho-Cheung Ng,Xinyu Niu,Wayne Luk,Peter Y. K. Cheung,George A. Constantinides

ACM Computing Surveys, no. 2 (2019): 1-39

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Real-Time Anomaly Detection for Flight Testing Using AutoEncoder and LSTM

Zhiqiang Que, Yanyang Liu, Ce Guo,Xinyu Niu,Yongxin Zhu,Wayne Luk

ICFPT, pp.379-382, (2019)

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Static Block Floating-Point Quantization for Convolutional Neural Networks on FPGA

Hongxiang Fan, Gang Wang, Martin Ferianc,Xinyu Niu,Wayne Luk

ICFPT, pp.28-35, (2019)

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Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going

Erwei Wang,James J. Davis, Ruizhe Zhao,Ho-Cheung Ng,Xinyu Niu,Wayne Luk,Peter Y. K. Cheung,George A. Constantinides

ACM Computing Surveys, no. 2 (2019): 40

Cited by1EIBibtex

Efficient Weight Reuse for Large LSTMs

Zhiqiang Que, Thomas Nugent, Shuanglong Liu, Li Tian, Xinyu Niu, Yongxin Zhu, Wayne Luk

ASAP, pp.17-24, (2019)

Cited by3EIBibtex

Hardware Compilation of Deep Neural Networks: An Overview

Ruizhe Zhao,Shuanglong Liu,Ho-Cheung Ng, Erwei Wang,James J. Davis,Xinyu Niu, Xiwei Wang, Huifeng Shi,George A. Constantinides,Peter Y. K. Cheung,Wayne Luk

ASAP, pp.1-8, (2018)

Cited by7EIBibtex

A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA

Hongxiang Fan,Shuanglong Liu, Martin Ferianc, Ho-Cheung Ng, Zhiqiang Que, Shen Liu,Xinyu Niu,Wayne Luk

FPT, pp.14-21, (2018)

Cited by10EIBibtex

Memory-Efficient Architecture for Accelerating Generative Networks on FPGA

Shuanglong Liu, Chenglong Zeng, Hongxiang Fan, Ho-Cheung Ng, Jiuxi Meng, Zhiqiang Que,Xinyu Niu,Wayne Luk

FPT, pp.30-37, (2018)

Cited by2EIBibtex

Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA

Shuanglong Liu, Hongxiang Fan,Xinyu Niu,Ho-Cheung Ng, Yang Chu,Wayne Luk

TRETS, no. 3 (2018)

Cited by8EIBibtex

Custom machine learning architectures: towards realtime anomaly detection for flight testing

Di Wu, Zhanrui Sun,Yongxin Zhu,Li Tian, Hanlin Zhu, Peng Xiong, Zihao Cao, Menglin Wang,Yu Zheng, Chao Xiong,Hao Jiang,Kuen Hung Tsoi

IPDPS Workshops, pp.1323-1330, (2018)

Cited by3EIBibtex

Correlation Coefficient Based Cluster Data Preprocessing and LSTM Prediction Model for Time Series Data in Large Aircraft Test Flights

Hanlin Zhu, Yongxin Zhu,Di Wu,Hui Wang,Li Tian,Wei Mao, Can Feng, Xiaowen Zha, Guobao Deng, Jiayi Chen,Tao Liu,Xinyu Niu

SmartCom, pp.376-385, (2018)

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Reconfigurable Hardware Generation for Tensor Flow Models of CNN Algorithms on a Heterogeneous Acceleration Platform

Jiajun Gao,Yongxin Zhu,Meikang Qiu, Kuen Hung Tsoi,Xinyu Niu,Wayne Luk, Ruizhe Zhao, Zhiqiang Que,Wei Mao, Can Feng, Xiaowen Zha, Guobao Deng

SmartCom, pp.87-96, (2018)

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Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation

Hongxiang Fan,Ho-Cheung Ng,Shuanglong Liu, Zhiqiang Que,Xinyu Niu,Wayne Luk

FPL, pp.287-294, (2018)

Cited by5EIBibtex

Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA

Ruizhe Zhao,Ho-Cheung Ng,Wayne Luk,Xinyu Niu

FPL, (2018)

Cited by15EIBibtex

A Low-Power Deconvolutional Accelerator for Convolutional Neural Network Based Segmentation on FPGA: Abstract Only

Shuanglong Liu,Xinyu Niu,Wayne Luk

FPGA, pp.293-211, (2018)

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Automatic Optimising CNN with Depthwise Separable Convolution on FPGA: (Abstact Only)

Ruizhe Zhao,Xinyu Niu,Wayne Luk

FPGA, pp.285-221, (2018)

Cited by6EIBibtex

Custom Framework for Run-Time Trading Strategies

Andreea-Ingrid Funie,Liucheng Guo,Xinyu Niu,Wayne Luk,Mark Salmon

ARC, pp.154-167, (2017)

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