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Umesh Gajanan Nawathe received the B.S. degree in electronics and telecommunication from the College of Engineering, University of Poona, India, and the M.S. degree in electrical engineering from the University of Michigan, Ann Arbor.
He is a Senior Manager with Sun Microsystems, Santa Clara, CA. Since joining Sun in 2003, he has worked on the Niagara series of microprocessors. His areas of interest include low-power and high-performance circuit design, clocking, design methodology, and process technology. Before joining Sun, he held senior technical and management positions working at MIPS/Silicon Graphics designing microprocessors based on the MIPS architecture, and at Intel prior to that. He has authored or co-authored and presented papers and seminars at the IEEE International Solid-State Circuits Conference (ISSCC), International Symposium of Physical Design (ISPD), and IEEE Santa Clara Valley Solid States Circuits Chapter.
Mr. Nawathe was the recipient of the Sun 2007 Chairman's Award for Innovation.
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CMOS PROCESSORS AND MEMORIESpp.3-27, (2010)
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