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1. Study on a High-Level Synthesis of Logic-in-Memory VLSI
A logic-in-memory VLSI architecture, in which small-capacity storage elements are distributed over a logic/arithmetic-circuit plane, has a potential advantage to perform highly parallel processing because the communnication between processing elements is localized.
In such a logic-in-memory VLSI architecture, the optimal scheduling and allocation methods to realize the highest-performance VLSI system under chip-area and/or power-dissipation constraints are disscussed.
2. Study on High-Performance Multiple-Valued VLSI Systems
Multiple-valued circuit-level logic-in-memory VLSI systems where storage elements are distributed over a logic-circuit plane
Low-power and high-performance VLSI systems based on the optimal control theory
Design of highly safe and self-checking VLSI systems
Asynchronous VLSI systems based on multiple-valued dual-rail coding
High-performance dual-rail current-mode multiple-valued logic circuit technologies
High-performance multiple-valued dynamic pass-transistor network using floating-gate MOS transistors and/or ferroelectric devices
1. Study on a High-Level Synthesis of Logic-in-Memory VLSI
A logic-in-memory VLSI architecture, in which small-capacity storage elements are distributed over a logic/arithmetic-circuit plane, has a potential advantage to perform highly parallel processing because the communnication between processing elements is localized.
In such a logic-in-memory VLSI architecture, the optimal scheduling and allocation methods to realize the highest-performance VLSI system under chip-area and/or power-dissipation constraints are disscussed.
2. Study on High-Performance Multiple-Valued VLSI Systems
Multiple-valued circuit-level logic-in-memory VLSI systems where storage elements are distributed over a logic-circuit plane
Low-power and high-performance VLSI systems based on the optimal control theory
Design of highly safe and self-checking VLSI systems
Asynchronous VLSI systems based on multiple-valued dual-rail coding
High-performance dual-rail current-mode multiple-valued logic circuit technologies
High-performance multiple-valued dynamic pass-transistor network using floating-gate MOS transistors and/or ferroelectric devices
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2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)pp.1-4, (2023)
IEEE Access (2023): 44923-44931
IEEE OPEN JOURNAL OF SIGNAL PROCESSING (2023): 452-461
Memories - Materials, Devices, Circuits and Systems (2023): 100035-100035
arXiv (Cornell University) (2023)
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2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)pp.1-4, (2023)
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