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Mitra, S.

Semicond. R&D Center, IBM, Essex Junction, VT, USA|c|

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Maximizing ESD design window by optimizing gate bias for cascoded drivers in 45nm and beyond SOI technologies

Souvick Mitra,Robert J Gauthier,Shunhua Chang,Junjun Li,Ralph Halbach, C Seguin

Electrical Overstress/ Electrostatic Discharge Symposium, pp.1-6E, (2010)

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