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个人简介
Dr. Shi-Yu Huang received his BS, MS degrees in Electrical Engineering from National Taiwan University in 1988, 1992 and Ph.D. degree in Electrical and Computer Engineering from the University of California, Santa Barbara in 1997, respectively.
From 1997 to 1998 he was a software engineer at National Semiconductor Corp., Santa Clara, investigating the system-on-a-chip design methodology. From 1998 to 1999, he was with Worldwide Semiconductor Manufacturing Corp., designing the high-speed Built-In Self-Test circuits for memories. He joined the faculty of National Tsing-Hua University, Taiwan, in 1999. Dr. Huang's research interests are mainly in design automation for VLSI, with the emphasis on formal verification, power estimation, fault diagnosis, and testing. More recently, he is also interested in the robust SRAM design for nanometer technologies and All-Digital Phase-Locked Loop (ADPLL) design. He served as the Program Co-Chair of IEEE Asian Test Symposium in 2004, and as the Program Chairs of IEEE International Workshop on Memory Technology, Design, and Testing in 2005 and 2006.
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