Souvick Mitra

Souvick Mitra received the M.Tech. degree from the Indian Institute of Technology, Kharagpur, in 1999, and the Ph.D. degree in electrical and computer engineering from George Mason University, Fairfax, VA, USA, in 2003. After completing his Ph.D., he joined IBM Semiconductor Research and Development Center and started working on the development of 90nm bulk compact models and led the 90nm low-power compact model activity. He is a Senior Manager-Deputy Director of GlobalFoundries, Essex Junction, VT, USA, managing a Global Team of ESD/LU engineers. Prior to this position, he was a Principal Member of Technical Staff with GlobalFoundries and before that, he was a Senior Engineer with IBM’s Systems and Technology Group. He has authored or coauthored more than 50 publications in journals and conferences and has been granted over 75 patents. His current interests are in ESD devices/solutions optimization for GlobalFoundries vast technology portfolio covering FinFETs to FDSOI to planar technologies for various applications like low voltage/digital, RF/HSS, and medium-high voltage. His external involvement outside of GlobalFoundries consists of serving as a Member, the Session Chair of Technical Program Committee, and a Moderator for EOS/ESD Symposium, International Reliability Symposium, and International SOI Conference for multiple years. He is currently on ESDA BoD and is also serving as the Technical Program Chair for 2020 EOS/ESD Symposium.